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Features
* Integrated PLL Loop Filter * ESD Protection (4 kV HBM/ 200 V MM; Except Pin 2: 4 kV HBM/ 100 V MM)
also at ANT1/ANT2
* High Output Power (8.0 dBm) with Low Supply Current (9.0 mA) * Modulation Scheme ASK/FSK * * * * * * * *
- FSK Modulation is Achieved by Connecting an Additional Capacitor Between the XTAL Load Capacitor and the Open Drain Output of the Modulating Microcontroller Easy to Design-in Due to Excellent Isolation of the PLL from the PA and Power Supply Single Li-cell for Power Supply Supply Voltage 2.0 V to 4.0 V in the Temperature Range of -40 C to 85 C/125 C Package TSSOP8L Single-ended Antenna Output with High Efficient Power Amplifier CLK Output for Clocking the Microcontroller One-chip Solution with Minimum External Circuitry 125 C Operation for Tire Pressure Systems
UHF ASK/FSK Transmitter T5753
Description
The T5753 is a PLL transmitter IC which has been developed for the demands of RF low-cost transmission systems at data rates up to 32 kBaud. The transmitting frequency range is 310 MHz to 330 MHz. It can be used in both FSK and ASK systems.
Figure 1. System Block Diagram
UHF ASK/FSK Remote control transmitter UHF ASK/FSK Remote control receiver
1 Li cell T5753 Encoder ATARx9x
XTO
PLL Antenna Antenna VCO
U3741B/ U3745B/ T5743/ T5744
Demod.
1...3 Control
Keys
IF Amp
PLL
XTO
Power amp.
LNA
VCO
Microcontroller
Rev. 4510F-RKE-07/04
Pin Configuration
Figure 2. Pinning TSSOP8L
CLK 1 8 ENABLE GND
PA_ENABLE
2 T5753
7
ANT2
3
6
VS
ANT1
4
5
XTAL
Pin Description
Pin Symbol Function Configuration
VS
1
CLK
Clock output signal for microcontroller The clock output frequency is set by the crystal to fXTAL/4
100 100
CLK
PA_ENABLE
50k
Uref = 1.1V
2
PA_ENABLE
Switches on power amplifier, used for ASK modulation
20 A
ANT1
3 4
ANT2 ANT1
Emitter of antenna output stage Open collector antenna output
ANT2
VS 1.5k 1.2k
VS
5
XTAL
Connection for crystal
XTAL
182 A
6 7 8
VS GND ENABLE
Supply voltage Ground Enable input
See ESD protection circuitry (see Figure 8 on page 8) See ESD protection circuitry (see Figure 8 on page 8)
ENABLE 200k
2
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T5753
Figure 3. Block Diagram
T5753
Power up/down CLK
f 4 f
32
ENABLE
1
8
PA_ENABLE
GND
2
PFD
7
CP ANT2 VS
3
LF
6
ANT1
XTAL
PA
4
VCO
XTO
5
PLL
General Description
This fully integrated PLL transmitter allows particularly simple, low-cost RF miniature transmitters to be assembled. The VCO is locked to 32 f XTAL hence a 9.8438 MHz crystal is needed for a 315 MHz transmitter. All other PLL and VCO peripheral elements are integrated. The XTO is a series resonance oscillator so that only one capacitor together with a crystal connected in series to GND are needed as external elements. The crystal oscillator together with the PLL needs typically < 3 ms until the PLL is locked and the CLK output is stable. There is a wait time of 3 ms until the CLK is used for the microcontroller and the PA is switched on. The power amplifier is an open-collector output delivering a current pulse which is nearly independent from the load impedance. The delivered output power is hence controllable via the connected load impedance. This output configuration enables a simple matching to any kind of antenna or to 50 . A high power efficiency of = Pout/(IS,PA VS) of 40% for the power amplifier results when an optimized load impedance of ZLoad = (255 + j192) is used at 3 V supply voltage.
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4510F-RKE-07/04
Functional Description
If ENABLE = L and the PA_ENABLE = L, the circuit is in standby mode consuming only a very small amount of current so that a lithium cell used as power supply can work for several years. With ENABLE = H the XTO, PLL and the CLK driver are switched on. If PA_ENABLE remains L only the PLL and the XTO is running and the CLK signal is delivered to the microcontroller. The VCO locks to 32 times the XTO frequency. With ENABLE = H and PA_ENABLE = H the PLL, XTO, CLK driver and the power amplifier are on. With PA_ENABLE the power amplifier can be switched on and off, which is used to perform the ASK modulation.
ASK Transmission
Th e T 57 5 3 i s a c t i v at e d b y E NA B L E = H . P A _ E NA B L E m us t r e ma i n L f or typically 3 ms, then the CLK signal can be taken to clock the microcontroller and the output power can be modulated by means of Pin PA_ENABLE. After transmission PA_ENABLE is switched to L and the microcontroller switches back to internal clocking. The T5753 is switched back to standby mode with ENABLE = L. Th e T 57 5 3 i s a c t i v at e d b y E NA B L E = H . P A _ E NA B L E m us t r e ma i n L f or typically 3 ms, then the CLK signal can be taken to clock the microcontroller and the power amplifier is switched on with PA_ENABLE = H. The chip is then ready for FSK modulation. The microcontroller starts to switch on and off the capacitor between the XTAL load capacitor and GND with an open-drain output port, thus changing the reference frequency of the PLL. If the switch is closed, the output frequency is lower than if the switch is open. After transmission PA_ENABLE is switched to L and the microcontroller switches back to internal clocking. The T5753 is switched back to standby mode with ENABLE = L. The accuracy of the frequency deviation with XTAL pulling method is about 25% when the following tolerances are considered. Figure 4. Tolerances of Frequency Modulation
FSK Transmission
~
VS CStray1
XTAL
CStray2 CM LM C0
Crystal equivalent circuit
RS
C4 C5 CSwitch
Using C4 = 8.2 pF 5%, C5 = 10 pF 5%, a switch port with CSwitch = 3 pF 10%, stray capacitances on each side of the crystal of C Stray1 = CStray2 = 1 pF 10%, a parallel capacitance of the crystal of C0 = 3.2 pF 10% and a crystal with CM = 13 fF 10%, an FSK deviation of 21.5 kHz typical with worst case tolerances of 16.25 kHz to 28.01 kHz results.
~
CLK Output
Clock Pulse Take-over
An output CLK signal is provided for a connected microcontroller, the delivered signal is CMOS compatible if the load capacitance is lower than 10 pF. The clock of the crystal oscillator can be used for clocking the microcontroller. Atmel's ATARx9x has the special feature of starting with an integrated RC-oscillator to switch on the T5753 with ENABLE = H, and after 1 ms to assume the clock signal of the transmission IC, so that the message can be sent with crystal accuracy.
4
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T5753
Output Matching and Power Setting The output power is set by the load impedance of the antenna. The maximum output power is achieved with a load impedance of ZLoad,opt = (255 + j192) . There must be a low resistive path to VS to deliver the DC current. The delivered current pulse of the power amplifier is 9 mA and the maximum output power is delivered to a resistive load of 400 if the 1.0 pF output capacitance of the power amplifier is compensated by the load impedance. An optimum load impedance of: ZLoad = 400 || j/(2 x 1.0 pF) = (255 + j192) thus results for the maximum output power of 8 dBm. The load impedance is defined as the impedance seen from the T5753's ANT1, ANT2 into the matching network. Do not confuse this large signal load impedance with a small signal input impedance delivered as input characteristic of RF amplifiers and measured from the application into the IC instead of from the IC into the application for a power amplifier. Less output power is achieved by lowering the real parallel part of 400 where the parallel imaginary part should be kept constant. Output power measurement can be done with the circuit of Figure 5. Note that the component values must be changed to compensate the individual board parasitics until the T5753 has the right load impedance ZLoad,opt = (255 + j192) . Also the damping of the cable used to measure the output power must be calibrated out. Figure 5. Output Power Measurement
VS
C1 = 1n L1 = 56n Power meter Z = 50 ZLopt ANT2 ~ C2 = 3.3p Rin 50
ANT1
Application Circuit
For the blocking of the supply voltage a capacitor value of C3 = 68 nF/X7R is recommended (see Figure 6 on page 6 and Figure 7 on page 7). C1 and C2 are used to match the loop antenna to the power amplifier where C 1 typically is 22 pF/NP0 and C2 is 10.8 pF/NP0 (18 pF + 27 pF in series); for C2 two capacitors in series should be used to achieve a better tolerance value and to have the possibility to realize the ZLoad,opt by using standard valued capacitors. C1 forms together with the pins of T5753 and the PCB board wires a series resonance loop that suppresses the 1st harmonic, hence the position of C1 on the PCB is important. Normally the best suppression is achieved when C1 is placed as close as possible to the pins ANT1 and ANT2. The loop antenna should not exceed a width of 1.5 mm, otherwise the Q-factor of the loop antenna is too high. L1 ([50 nH to 100 nH) can be printed on PCB. C4 should be selected that the XTO runs on the load resonance frequency of the crystal. Normally, a value of 12 pF results for a 15 pF load-capacitance crystal.
~
5
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Figure 6. ASK Application Circuit
S1 BPXY
ATARx9x
VDD
1
VSS
20
VS
S2
BPXY
BPXY
OSC1
BPXY
7
T5753
Power up/down
CLK
1
f 4 f
32
ENABLE
8
PA_ENABLE
GND
2
PFD
7
C3
C2 CP ANT2 VS
3
LF
6
VS
Loop Antenna
C1
XTAL
ANT1
XTAL
PA
4
L1
VCO
XTO
5 C4
PLL
VS
6
T5753
4510F-RKE-07/04
T5753
Figure 7. FSK Application Circuit
ATARx9x
S1 BPXY
VDD
1
S2 BPXY VSS
20
VS
BPXY
BP42/T2O 18
OSC1
BPXY
7
T5753
Power up/down
CLK
1
f 4 f
32
ENABLE
8
PA_ENABLE
GND
2
PFD
7
C3
C2 CP ANT2 VS
3
LF
6
VS
Loop Antenna
C1
ANT1
XTAL XTAL
PA
C5 C4
4
L1
VCO
XTO
5
PLL
VS
7
4510F-RKE-07/04
Figure 8. ESD Protection Circuit
VS ANT1
CLK
PA_ENABLE
ANT2
XTAL
ENABLE
GND
Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Supply voltage Power dissipation Junction temperature Storage temperature Ambient temperature Input voltage Note: Symbol VS Ptot Tj Tstg Tamb VmaxPA_ENABLE -55 -55 -0.3 Minimum Maximum 5 100 150 125 125 (VS + 0.3)
(1)
Unit V mW C C C V
1. If VS + 0.3 is higher than 3.7 V, the maximum voltage will be reduced to 3.7 V.
Thermal Resistance
Parameters Junction ambient Symbol RthJA Value 170 Unit K/W
8
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T5753
Electrical Characteristics
VS = 2.0 V to 4.0 V, Tamb = -40 C to 125 C unless otherwise specified. Typical values are given at VS = 3.0 V and Tamb = 25 C. All parameters are referred to GND (pin 7).
Parameters Test Conditions Power down, VENABLE < 0.25 V, -40 C to 85 C VPA-ENABLE < 0.25 V, -40C to +125 C VPA-ENABLE < 0.25 V, 25C (100% correlation tested) Power up, PA off, VS = 3 V, VENABLE > 1.7 V, VPA-ENABLE < 0.25 V Power up, VS = 3.0 V, VENABLE > 1.7 V, VPA-ENABLE > 1.7 V VS = 3.0 V, Tamb = 25 C, f = 315 MHz, ZLoad = (255 + j192) W Tamb = -40 C to +85 C, VS = 3.0 V VS = 2.0 V Tamb = -40C to +125C, VS = 3.0 V VS = 2.0 V, POut = PRef + PRef Selectable by load impedance fCLK = f0/128 Load capacitance at Pin CLK = 10 pF fO 1 x fCLK fO 4 x fCLK other spurious are lower fXTO = f0/32 fXTAL = resonant frequency of the XTAL, CM 10 fF, load capacitance selected accordingly Tamb = -40 C to +85 C, Tamb = -40 C to +125 C Referred to fPC = fXT0, 25 kHz distance to carrier 25 kHz distance to carrier at 1 MHz at 36 MHz fVCO 310 f0/128 CLoad 10 pF V0h V0l Rs VS x 0.8 VS x 0.2 110 7 Symbol Min. Typ. Max. 350 7 <10 Unit nA A nA
Supply current
IS_Off
Supply current Supply current Output power Output power variation for the full temperature range
IS IS_Transmit PRef PRef PRef PRef PRef POut_typ 0 6.0
3.7 9 8.0
4.8 11.6 10.5
mA mA dBm
-1.5 -4.0 -2.0 -4.5 8.0
dB dB dB dB dBm
Output power variation for the full temperature range Achievable output-power range
Spurious emission
-55 -52
dBc dBc
Oscillator frequency XTO (= phase comparator frequency)
fXTO -30 -40 fXTAL 250 -116 -86 -94 -125 -110 -80 -90 -121 330 +30 +40 ppm ppm kHz dBc/Hz dBc/Hz dBc/Hz dBc/Hz MHz MHz V V pF
PLL loop bandwidth Phase noise of phase comparator In loop phase noise PLL Phase noise VCO Frequency range of VCO Clock output frequency (CMOS microcontroller compatible) Voltage swing at Pin CLK Series resonance R of the crystal Capacitive load at Pin XT0 Note: 1. If VS is higher than 3.6 V, the maximum voltage will be reduced to 3.6 V.
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Electrical Characteristics (Continued)
VS = 2.0 V to 4.0 V, Tamb = -40 C to 125 C unless otherwise specified. Typical values are given at VS = 3.0 V and Tamb = 25 C. All parameters are referred to GND (pin 7).
Parameters FSK modulation frequency rate ASK modulation frequency rate Test Conditions Duty cycle of the modulation signal = 50% Duty cycle of the modulation signal = 50% Low level input voltage High level input voltage Input current high Low level input voltage High level input voltage Input current high VIl VIh IIn VIl VIh IIn Symbol Min. 0 0 Typ. Max. 32 32 0.25 1.7 20 1.7 0.25 VS(1) 5 Unit kHz kHz V V A V V A
ENABLE input
PA_ENABLE input Note:
1. If VS is higher than 3.6 V, the maximum voltage will be reduced to 3.6 V.
10
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4510F-RKE-07/04
T5753
Ordering Information
Extended Type Number T5753-6AQ Package TSSOP8L Remarks Taped and reeled, Marking: T573
Package Information
11
4510F-RKE-07/04
Revision History
Changes from Rev. 4510E-RKE-10/03 to Rev. 4510F-RKE-07/04
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. 1. Abs. Max. Ratings table (page 8): row "Input voltage" added 2. Abs. Max. Ratings table (page 8): table note 1 added 3. El. Char. table (page 10): row "PA_ENABLE input" changed 4. El. Char. table (page 10): table note 1 added 5. Ordering Information table (page 11): Remarks changed
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4510F-RKE-07/04

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